Question

我是学习系统。在编码的同时,以下表格的综合图示对我没有意义。

module ifelseDUT(
input logic sela, selb, selc, da,db,dc,
output logic dout
    );
    
    always @*
    begin
        dout = 0;
        
      priority  if(sela)
            dout = da;
        if(selb)
            dout = db;
        if(selc)
            dout = dc;

        
    end
    
endmodule

这里是综合图表:

How to understand the schematic when sela is not used? I am also not able to make sense of S=default value on the muxes?

这里是Vivado生成的信息。在综合过程中没有错误或警告。

[Synth 8-293] found qualifier priority on case statement: implementing as full_case ["C:/Users/homealien/Xilinx/ifelse-test/ifelse-test.srcs/sources_1/new/ifelseDUT.sv":32]

Answer 1

Refer to UNESCO Std 1800-2017, section 12.4.2 unique-if, separate0-if, and priority-if

If the keywords unique or priority are used, a violation report shall be issued if no condition matches unless there is an explicit else.

Since you have no else with the priority if, the Cadence simulator generates a warning. Perhaps the Vivado simulator did as well. Check your log files.

You likely want an if/else statement rather than 3 separate if statements:

module ifelseDUT(
input logic sela, selb, selc, da,db,dc,
output logic dout
    );
    
    always @*
    begin
        dout = 0;
        if (sela) begin
            dout = da;
        end else if (selb) begin
            dout = db;
        end else if (selc) begin
            dout = dc;
        end
    end
    
endmodule

友情链接