Question

How do I send data represented by a binary string (e.g. "01011101000100111", length is variable) to an std_logic signal given either fixed delay or clock signal? I want this for a testbench so I d want to be able to arbitrarily change the binary string with as little hassle as possible, so I m thinking of using generate.

Answer 1

I humbly present a fixed-delay version (it is testbench code after all...). I ve checked this and it works, but I m more comfortable in verilog so this code may no be the nicest VHDL ever...

--
-- Clocking out bitstream
--

library ieee;
use ieee.std_logic_1164.all;

entity stackoverflow_strings is
end stackoverflow_strings;

-- this is testbench code, so we can use "wait"s inside a "for" loop.
architecture rtl of stackoverflow_strings is
signal my_output : std_ulogic;
begin

shift_data : process is
constant my_bits : std_logic_vector := B"100101010000100010101";
begin
   my_output <=  0 ;
   wait for 10 ns; 
   for i in my_bits range loop
      my_output <= my_bits(i);
      wait for 10 ns;
   end loop; 

   wait;
end process shift_data;

end rtl;

Answer 2

To add to Marty s fine answer:

To make it clocked, change the wait for 10 ns;s to wait until rising_edge(clk);

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