这是一个令人感兴趣的问题。 面对这一点,人们会认为,自以来,该编码是一份连续的指令,它冲动了以前的记本,而且所有内容都很好。 即便如此,引用手册:

These instructions force the processor to complete all modifications to flags, registers, and memory by previous instructions and to drain all buffered writes to memory before the next instruction is fetched and executed.

(Emphasis mine)

It doesn t say anything about the ordering with respect to sending the IPI as that is part of the current instruction, not the next one. So this theoretically means the other core could execute the mov r1, [ _x] while the originating core is still busy flushing stuff but is very unlikely given that the target core would need to service the interrupt which probably has a lot higher latency.

如“@harold”所述,这一点是空洞的,因为“WRMSR并非总是序列化。 阅读我最初错过的脚注:

WRMSR to the IA32_TSC_DEADLINE MSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.

因此,绝对不能保证转录到<条码>x的文字。

来自Intel® 64和I-32建筑软件开发商手册第3A卷:系统方案拟订指南,第一部分

11.12.3 MSR Access in x2APIC Mode

To allow for efficient access to the APIC registers in x2APIC mode, the serializing semantics of WRMSR are relaxed when writing to the APIC registers. Thus, system software should not use “WRMSR to APIC registers in x2APIC mode” as a serializing instruction. Read and write accesses to the APIC registers will occur in program order. A WRMSR to an APIC register may complete before all preceding stores are globally visible; software can prevent this by inserting a serializing instruction or the sequence MFENCE;LFENCE before the WRMSR.

The RDMSR instruction is not serializing and this behavior is unchanged when reading APIC registers in x2APIC mode. System software accessing the APIC registers using the RDMSR instruction should not expect a serializing behavior. (Note: The MMIO-based xAPIC interface is mapped by system software as an un-cached region. Consequently, read/writes to the xAPIC-MMIO interface have serializing semantics in the xAPIC mode.)

然而,我仍然不知道这是否会与友好进程者合作。

加工商1在英特尔邮联处理国际消费物价指数时,有可能遵守加工商0撰写的价值。 保证在向X2APIC移交独立会计师事务所之前必须设置一个障碍,因为写作X2APIC MSRs不是《英特尔公司指令》的序列。

AMD CPUs don t need a fence after writing x2APIC/TSC_DEADLINE MSRs.

这里指的是在跨核心职能要求时的欧伦特角守则。 在向目标CPU派遣IPI之前,它有“历史;存在”。 对AMD CPUs来说,软弱无力的休眠是一例。

static void x2apic_send_IPI(int cpu, int vector)
{
    u32 dest = per_cpu(x86_cpu_to_apicid, cpu);

    /* x2apic MSRs are special and need a special fence: */
    weak_wrmsr_fence();
    __x2apic_send_IPI_dest(dest, vector, APIC_DEST_PHYSICAL);
}

/*
 * Make previous memory operations globally visible before
 * a WRMSR.
 *
 * MFENCE makes writes visible, but only affects load/store
 * instructions.  WRMSR is unfortunately not a load/store
 * instruction and is unaffected by MFENCE.  The LFENCE ensures
 * that the WRMSR is not reordered.
 *
 * Most WRMSRs are full serializing instructions themselves and
 * do not require this barrier.  This is only required for the
 * IA32_TSC_DEADLINE and X2APIC MSRs.
 */
static inline void weak_wrmsr_fence(void)
{
    alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE));
}