Question

每个人。

I am designing a digital clock in VHDL which I am supposed to synthesize on a FPGA . I am cascading S1,S2,M1,M2,H1 and H2 where (S1 = second 1, M1 = Minute 1, H1 = hour 1 etc.). One of the requirements is for the clock to switch between 24HR display to a 12HR display format. How do I do it given that H1 and H2 are represented by 4 bits each i.e. 8 bits in total to display the current hour. Will I need to concatenate HR1 and HR2 and then subtract 12 and then de-concatenate it again? keep in mind that X mod 12 is not a synthesizable operation for implementation in FPGA.

非常感谢。

Answer 1

基本上,你在双字母缩略语中做了全部算术。因此,仅建造一个BCD比较器/分机:

if h1 = 1 and h2 > 2
  subtract 1 off h1
  subtract 2 off h2
  if h2 wrapped
     subtract 1 off h1

不需要 mo!

Answer 2

如果你有其他资源,你可以把H类登记册增加一倍。让我们把H24-1和H24-2(如你已经做的那样)以及H12-1和H12-2“mod12”登记在旁。两把奶制品都将被锁定,因此,每24小时都有两种格式。有色人只是利用一些未爆炸弹药来交换其中一部分。

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