这是我的“design.sv”和“testbench.sv”的代码。
module FAunit(
input x_0, y_0, c_0,
output sum_0, c_1
);
wire a_1, a_2, a_3, a_4;
wire b_1, b_2, b_3;
assign a_1 = x_0 & ~y_0 & ~c_0;
assign a_2 = ~x_0 & y_0 & ~c_0;
assign a_3 = x_0 & y_0 & c_0;
assign a_4 = ~x_0 & ~y_0 & c_0;
assign s_0 = a_1 | a_2 | a_3 | a_4;
assign b_1 = x_0 & y_0;
assign b_2 = y_0 & c_0;
assign b_3 = x_0 & c_0;
assign c_1 = b_1 | b_2 | b_3;
endmodule >single unit consisting four_bit_fulladder
module four_bit_fulladder(
input [3:0] X, Y,
output [3:0] sum,
output[4:0] carry
);
assign carry[0] = 0;
FAunit unit_0(
.x_0(X[0]),
.y_0(Y[0]),
.c_0(carry[0]),
.sum_0(sum[0]),
.c_1(carry[1])
);
FAunit unit_1(
.x_0(X[1]),
.y_0(Y[1]),
.c_0(carry[1]),
.sum_0(sum[1]),
.c_1(carry[2])
);
FAunit unit_2(
.x_0(X[2]),
.y_0(Y[2]),
.c_0(carry[2]),
.sum_0(sum[2]),
.c_1(carry[3])
);
FAunit unit_3(
.x_0(X[3]),
.y_0(Y[3]),
.c_0(carry[3]),
.sum_0(sum[3]),
.c_1(carry[4])
);
endmodule > going to be instantiated on "testbench.sv"
设计.sv
module test_bench;
wire [3:0] X, Y;
reg [3:0] SUM;
reg [4:0] CARRY;
assign X = 4 b1101, Y = 4 b1011;
four_bit_fulladder ohgod(
.X(X),
.Y(Y),
.sum(SUM),
.carry(CARRY)
);
initial
begin
#5
$display("X: %b
", X);
$display("Y: %b
", Y);
$display("sum: %b
", SUM);
$display("carry: %b", CARRY[4]);
#5;
end
endmodule
<testbench.sv>
34 sdf=0)
# KERNEL: ASDB file was created in location /home/runner/dataset.asdb
# KERNEL: X: 1101
# KERNEL:
# KERNEL: Y: 1011
# KERNEL:
# KERNEL: sum: zzzz
# KERNEL:
# KERNEL: carry: 1
记录
我试图在“design.sv”上从模块实例化到“testbench.sv”，然后进行系统任务。但是，总和的值显示出来与应该的不同（“4 b1000”）。
我如何确定这一守则,以便正确推动系统的任务?