I have a problem in SystemC trying to write a signal after some time passes... Consider the following: process (clk) begin -- Updating my signal, out signal, in order to get result, but ...

I am a beginner in SystemC programming and there is one thing I noticed (looking in the SystemC official documentation): all types that I used to deal with in VHDL simulations have not been "ported" ...

I m using C++ for hardware-based model design with SystemC. SystemC as a C++ extension introduces specific datatypes useful for signal and byte descriptions. How can I access the first bits of a ...

I am having a repeating seg fault while using SystemC. During initialization I set a value to 0. During operation of a testbench I am setting this value to 1 in a module (proc). This is a sc_signal ...

System C provides arbitrary length integer types that can be manipulated either as numbers (i.e. with support for artihmetic) or as bit-vectors (i.e. with support for logic operations and working with ...

Does System C support tri-state logic? That is, bits that can get 0, 1 or X, where X means "unknown"? If it does, does it also support vectors that can contain Xes, including logic and arithmetic ...

When I tried to install the SCV library, I came accross with the following problem: "checking build system type... Invalid configuration x86_64-unknown-linux-gnu : machine x86_64-unknown not ...

Hardware design with VHDL or Verilog is more like programming nowadays. However, I see SO members are not so actively talking about VHDL/Verilog programming. Is there any forum dealing with hardware ...