Question

How to delay signal for a given number of cycles in VHDL? Number of cycles is given as a generic.

任何其他备选办法

process(CLK) is
begin
  if rising_edge(CLK) then
    a_q <= a;
    a_q_q <= a_q;
    a_q_q_q <= a_q_q;
    -- etc
  end if;
end process;

?

Answer 1

创建1-d阵列(简称a_store<>/code>),以适当类型的信号,其阵列的长度与周期数有关。这可能意味着,除非已经存在一种病媒:例如<代码>std_logic_vector或integer_vector (后者只在VHDL-2008年才成为标准)。



接着,每一行各样阵列:

if rising_edge(clk) then
  a_store <= a_store(store high-1 downto 0) & a;
  a_out <= a_store(a_store high);
end if;