Question

I m 创立一个称为甲型六氯环己烷的新项目,创建新的档案测试。

library ieee;
use ieee.std_logic_1164.all;

entity d_latch is 
port(
data_in:in std_logic;
data_out:out std_logic;
enable:in std_logic);
end d_latch;

architecture beh of d_latch is 
begin
process(data_in,enable)
    begin
     if(enable <=  1 ) then 
        data_out <= data_in;
      end if;
    end process;
end beh;

I add test.vhd to the project alpha then i compile the file.After that i simulate->start simulate then i check [+] work library then the module presented in it,but an error s message appears

Error loading design

Answer 1

第一,说明是否取得正确结果:

if (enable <= 1 > must be if(enable = 1

I simulated your code and no errors found. Simulation results was correct.

Just open modelsim software, click file and change directory (for example to the address of test.vhd file) Then compile test.vhd and simulate it. Sometimes you should close modelsim and do the same stages again, because the library directory may be changed wrongly by yourself.

Answer 2

I ve had similar problems with Modelsim, even when just making minor changes to the VHDL code and recompiling. One thing that seems to work is to change the port modes from buffer to out or inout, depending on the design.

友情链接