So this is more of a generic question. I seem to keep finding myself being put on larger and larger projects. Recently I have been assigned to a very large project written in C and VHDL. The goal ...

There was this problem that has been asked about implementing a load byte into a single cycle datapath without having to change the data memory, and the solution was something below. alt text http://...

IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV ...

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Consider : process(a) According to the text i have : A process is first entered at the time of simulation, at which time it is executed until it suspends itself due to a wait statement or a ...

How do I send data represented by a binary string (e.g. "01011101000100111", length is variable) to an std_logic signal given either fixed delay or clock signal? I want this for a testbench so I d ...

What programming language has short and beautiful grammars (in EBNF)? Some languages are easer to be parsed. Some time ago I have created a simple VHDL parser, but it was very slow. Not because it is ...

I m currently writing a 32Bit ALU (Add/Sub) in VHDL. I ve got a problem with the overflow bit. I can t see when to set the overflow depending on the operation (addition, subtraction) and the input ...